Clock buffer circuit and clock signal buffering method which can suppress current consumption

ABSTRACT

A clock buffer circuit includes an amplifier section and a control section. The amplifier section amplifies a clock signal in response to a control signal. The control section generates the control signal based on an amplitude of the clock signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a clock buffer circuit and a clocksignal buffering method which amplify a clock signal sent to asemiconductor integrated circuit. More particularly, the presentinvention relates to a clock buffer circuit and a clock signal bufferingmethod which can suppress current consumption.

2. Description of the Related Art

Conventionally, an amplitude of a clock signal sent to a semiconductorintegrated circuit is different depending on a supply source of theclock signal. Thus, the clock signal may have an amplitude that issufficiently large for the operation of the semiconductor integratedcircuit or have an amplitude which is not sufficiently large enough forthe operation of the semiconductor integrated circuit.

Therefore, a clock buffer circuit is used to amplify the clock signalwhich is not sufficiently large for the operation of the semiconductorintegrated circuit. In the clock buffer circuit, when the clock signalis inputted which is not sufficiently large for the operation of thesemiconductor integrated circuit, the clock signal is amplified to thesufficiently high level for the operation of the semiconductorintegrated circuit, and the amplified clock signal is inputted to thesemiconductor integrated circuit.

However, in a conventional clock buffer circuit, a feedback loop isexecuted. In this case, even if a clock signal is inputted whoseamplitude is large enough that it doesn't need to be amplified, acurrent corresponding to the clock signal flows through the feedbackloop. This results in the useless consumption of electrical power by thecurrent.

Japanese Laid Open Patent Application (JP-A-Heisei 8-130462) discloses aclock buffer circuit as described below. That is, the clock buffercircuit includes a first buffer circuit, a second buffer circuit, aswitching circuit and a switch control circuit. The first buffer circuitperforms a buffer operation to a first clock signal. The second buffercircuit performs a buffer operation to a second clock signal which is aninverse signal to the first clock signal. The switching circuit isconnected between a first clock signal output line connected with anoutput end of the first buffer circuit, and a second clock signal outputline connected with an output end of the second buffer circuit. Theswitch control circuit operates such that the switching circuit isconducting for a predetermined period when the first and second clocksignals are inverted relative to each other, and the switching circuitis not conducting for a period other than the predetermined period.

In the clock buffer circuit, when the first clock signal is invertedfrom L to H, a part of charges accumulated in parasitic capacitance ofthe first clock signal output line is transferred through the switchingcircuit to the side of the second clock signal output line. On the otherhand, when the second clock signal is inverted from L to H, a part ofcharges accumulated in parasitic capacitance of the second clock signaloutput line is transferred through the switching circuit to the side ofthe first clock signal output line. As mentioned above, the part of thecharges transferred from the parasitic capacitance of the first (second)clock signal output line is used effectively, when the second (first)clock signal is inverted. Correspondingly, the charges (current) to besupplied to the second (first) clock signal output line can besuppressed, when the second (first) clock signal is inverted.

However, the clock buffer circuit disclosed in the above-mentioned priorart cannot suppress the useless consumption of the current, when theclock signal whose amplitude is large enough to operate thesemiconductor integrated circuit is inputted to the clock buffercircuit.

SUMMARY OF THE INVENTION

The present invention is made to solve the above-described problems inthe related arts as mentioned above.

An object of the present invention is to provide a clock buffer circuitin which a useless current is not consumed if a clock signal having asufficiently high amplitude for an operation of a semiconductorintegrated circuit is inputted.

In order to achieve an aspect of the present invention, a clock buffercircuit includes an amplifier section for amplifying a clock signal inresponse to a control signal, and a control section for generating thecontrol signal based on an amplitude of the clock signal.

In order to achieve another aspect of the present invention, the controlsection includes an amplitude detecting section for detecting theamplitude of the clock signal, a comparator for comparing the amplitudeof the clock signal with a predeterminied value, and a control signalgenerating section for generating the control signal based on thecomparison result.

In this case, the amplifier section includes an amplifier for inputtingthe clock signal, a line connected between an output and an input of theamplifier, and a switching section provided on the line, and wherein theswitching section is turned ON/OFF in response to the control signal.

Also, the switching section includes a P channel MOS transistor and an Nchannel MOS transistor. In this case, a source of the P channel MOStransistor is connected to a source of the N channel MOS transistor anda drain of the P channel MOS transistor is connected to a drain of the Nchannel MOS transistor, and wherein an inverter is connected to one of agate of the P channel MOS transistor and a gate of the N channel MOStransistor, and the control signal is inputted to the inverter and tothe other of the gate of the P channel MOS transistor and the gate ofthe N channel MOS transistor.

Further the amplitude detecting section includes a high level detectingsection for detecting a peak voltage in a high level of the clocksignal, a low level detecting section for detecting a bottom voltage ina low level of the clock signal, and a voltage difference detectingsection for detecting a voltage difference between the peak voltage andthe bottom voltage as the amplitude of the clock signal.

In this case, the amplitude detecting section may include a smoothingcircuit for smoothing the clock signal to convert it into a directcurrent voltage corresponding to the amplitude of the clock signal.

Also, the control signal generating section includes a flip-flop, andwherein the flip-flop includes a clock input terminal to which a signalindicative of the comparison result is inputted, a data input terminalto which a data input signal corresponding to a power supply voltage isinputted, a reset input terminal to which a reset signal is inputted,and an inversion output terminal, and wherein the flip-flop outputs thecontrol signal from the inversion output terminal based on the signalindicative of the comparison result, the data input signal and the resetsignal.

In order to achieve a still another aspect oh the present invention, aclock signal buffering method includes the steps of comparing a clocksignal with a reference signal to generate a control signal generatingsignal based on the comparison result, generating a control signal basedon the control signal generating signal, and outputting the clock signalin response to the control signal.

Also, the comparing step includes detecting an amplitude of the clocksignal, and comparing the amplitude of the clock signal with apredetermined value corresponding to the reference signal to generatethe control signal generating signal based on the comparison result.

Further, the step of detecting the amplitude of the clock signalincludes detecting a peak voltage in a high level of the clock signal,detecting a bottom voltage in a low level of the clock signal, anddetecting a voltage difference between the peak voltage and the bottomvoltage as the amplitude of the clock signal.

In this case, the step of detecting the amplitude of the clock signalmay include smoothing the clock signal to convert it into a directcurrent voltage corresponding to the amplitude of the clock signal.

Also, the step of outputting the clock signal includes providing anamplifier to which the clock signal is inputted, providing a lineconnected between an output and an input of the amplifier, providing aswitching section provided on the line, and turning the switchingsection ON/OFF in response to the control signal.

In order to achieve a yet still another aspect of the present invention,a clock buffer circuit includes a unit for comparing a clock signal witha reference signal to generate a control signal generating signal basedon the comparison result, a unit for generating a control signal basedon the control signal generating signal, and a unit for outputting theclock signal in response to the control signal.

In this case, the comparing unit includes a unit for detecting anamplitude of the clock signal, and a unit for comparing the amplitude ofthe clock signal with a predetermined value corresponding to thereference signal to generate the control signal generating signal basedon the comparison result.

Also, the unit for detecting the amplitude of the clock signal includesa unit for detecting a peak voltage in a high level of the clock signal,a unit for detecting a bottom voltage in a low level of the clocksignal, and a unit for detecting a voltage difference between the peakvoltage and the bottom voltage as the amplitude of the clock signal.

Further, the unit for detecting the amplitude of the clock signalsmooths the clock signal to convert it into a direct current voltagecorresponding to the amplitude of the clock signal.

In this case, the unit for outputting the clock signal may include aunit for providing an amplifier to which the clock signal is inputted, aunit for providing a line connected between an output and an input ofthe amplifier, a unit for providing a switching section arranged on theline, and a unit for turning the switching section ON/OFF in response tothe control signal.

Also, a clock buffer circuit includes an amplifier section foramplifying a clock signal, and a control section for generating acontrol signal based on an amplitude of the clock signal, and wherein afeedback loop which can be set in one of an opened state and aconductive state is arranged in the amplifier section and the feedbackloop is set selectively in one of the opened state and the conductivestate based on the control signal.

Further, the control section includes an amplitude detecting section fordetecting the amplitude of the clock signal, a comparator for comparingthe amplitude of the clock signal with a predetermined value, and acontrol signal generating section for generating the control signalbased on the comparison result.

In this case, the amplitude detecting section includes a high leveldetecting section for detecting a peak voltage in a high level of theclock signal, a low level detecting section for detecting a bottomvoltage in a low level of the clock signal, and a voltage differencedetecting section for detecting a voltage difference between the peakvoltage and the bottom voltage as the amplitude of the clock signal.

Also, the amplitude detecting section includes a smoothing circuit forsmoothing the clock signal to convert into a direct current voltagecorresponding to the amplitude of the clock signal.

Further, the control signal generating section includes a flip-flop, andwherein the flip-flop includes a clock input terminal to which a signalindicative of the comparison result is inputted, a data input terminalto which a data input signal corresponding to a power supply voltage isinputted, a reset input terminal to which a reset signal is inputted,and an inversion output terminal, and wherein the flip-flop outputs thecontrol signal from the inversion output terminal based on the signalindicative of the comparison result, the data input signal and the resetsignal.

In order to achieve another aspect of the present invention, a clockbuffer circuit includes an output section for receiving a clock signal,and selectively outputting one of the clock signal and an amplifiedclock signal obtained by amplifying the clock signal in response to acontrol signal, and a control section for generating the control signalbased on an amplitude of the clock signal, and wherein the outputsection includes an amplifier for amplifying the clock signal, and abypassing section for bypassing the amplifier for the clock signal inresponse to the control signal to prevent the amplifier from beingoperated.

In order to achieve still another aspect of the present invention, aclock buffer circuit includes a input section for inputting a clocksignal, and a control section for controlling a signal path for theclock signal to be set in one of a conductive state and a non-conductivestate based on an amplitude of the clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the teachings of the present inventionmay be acquired by referring to the accompanying figures, in which likereference numbers indicate like features and wherein:

FIG. 1 is a circuit block diagram showing an example of a clock buffercircuit in the present invention;

FIG. 2 is a circuit diagram showing a structure example of an amplifiersection shown in FIG. 1;

FIG. 3 is a block diagram showing a structure example of an amplitudedetecting section shown in FIG. 1;

FIG. 4A is a timing chart showing a level of a reset signal RST in theclock buffer circuit of this embodiment;

FIG. 4B is a timing chart showing a level of a clock signal CLK in theclock buffer circuit of this embodiment;

FIG. 4C is a timing chart showing a level of an amplitude detectionvoltage Va in the clock buffer circuit of this embodiment;

FIG. 4D is a timing chart showing a level of a clock input signal CRSoutputted from a comparator in the clock buffer circuit of thisembodiment;

FIG. 4E is a timing chart showing a level of a control signal CONToutputted from a flip-flop in the clock buffer circuit of thisembodiment;

FIG. 5A is a timing chart showing a level of the reset signal RST in theclock buffer circuit of this embodiment;

FIG. 5B is a timing chart showing another level of the clock signal CLKin the clock buffer circuit of this embodiment;

FIG. 5C is a timing chart showing another level of the amplitudedetection voltage Va in the clock buffer circuit of this embodiment;

FIG. 5D is a timing chart showing another level of the clock inputsignal CRS outputted from the comparator in the clock buffer circuit ofthis embodiment;

FIG. 5E is a timing chart showing another level of the control signalCONT outputted from the flip-flop in the clock buffer circuit of thisembodiment;

FIG. 6 is a block diagram showing another structure example of theamplitude detecting section shown in FIG. 1; and

FIG. 7 is a circuit diagram showing a variation example of thisembodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to drawings, various preferred embodiments of the presentinvention will be described.

Embodiments of the present invention will be described below withreference to the attached drawings.

FIG. 1 is a circuit block diagram showing an embodiment of a clockbuffer circuit in the present invention.

As shown in FIG. 1, a clock buffer circuit 50 in this embodiment isprovided with an amplifier section 1, an amplitude detecting section 2,a comparator (a comparing device) 3 and a flip-flop 4.

The amplifier section 1 and the amplitude detecting section 2 areconnected in parallel. A clock signal CLK is inputted to both theamplifier section 1 and the amplitude detecting section 2. An innercircuit (the semiconductor integrated circuit) is connected in series toa next stage of the amplifier section 1. The comparator 3 is connectedin series to a next stage of the amplitude detecting section 2. Theflip-flop 4 is connected in series to a next stage of the comparator 3.An output section of the flip-flop 4 is connected in series to theamplifier section 1.

The amplifier section 1 amplifies the clock signal CLK inputted from theoutside of the clock buffer circuit 50 to provide an output to an innercircuit.

The amplitude detecting section 2 inputs the clock signal CLK from theoutside to generate a voltage corresponding to an amplitude of the clocksignal CLK, and to output a signal indicative of the voltage value as anamplitude signal Va.

The comparator 3 compares the voltage corresponding to the amplitudesignal Va outputted from the amplitude detecting section 2 with apredetermined comparison voltage VREF. The comparator 3 outputs acomparison result signal (a control signal generating signal) CRSindicative of the comparison result.

The flip-flop 4 receives the comparison result signal CRS outputted fromthe comparator 3, as a clock input signal CRS, from a clock inputterminal C. The flip-flop 4 receives an H level signal corresponding toa power supply voltage VDD, as a data input signal H, from a data inputterminal D. The flip-flop 4 receives a reset signal RST inputted fromthe outside of the clock buffer circuit 50, from a reset input terminalR. The flip-flop 4 outputs, as a control signal CONT, a signal outputtedfrom an inversion output terminal (/Q), based on the clock input signalCRS, the data input signal H and the reset signal RST.

The amplifier section 1 receives the clock signal CLK from the outside,and amplifies the clock signal CLK in response to the control signalCONT outputted from the flip-flop 4 to output the amplified clock signalCLK to the inner circuit.

FIG. 2 is a circuit diagram showing a structure example of the amplifiersection 1 shown in FIG. 1.

As shown in FIG. 2, the amplifier section 1 includes an invertingamplifier 11, an inverter 12 and an analog switch 15.

The inverting amplifier 11 inverts and amplifies the clock signal CLKinputted from the outside to output to the inner circuit.

The inverter 12 inverts the control signal CONT inputted from theflip-flop 4 to output to the analog switch 15.

In the analog switch 15, the ON/OFF state of the analog switch 15 isswitched, based on the control signal CONT outputted from the flip-flop4 and the signal outputted from the inverter 12. As the ON/OFF state ofthe analog switch 15 is switched, a feedback loop 17 of the invertingamplifier 11 is generated, or the feedback loop 17 is cut off.

In the analog switch 15, an input terminal of the analog switch 15 isconnected to an output side of the inverting amplifier 11, and an outputterminal of that is connected to an input side of the invertingamplifier 11. The analog switch 15 includes of a P channel MOStransistor 13 and an N channel MOS transistor 14. A source of thetransistor 13 is connected to a source of the transistor 14, and a drainof the transistor 14 is connected to a drain of the transistor 13. Aninversion signal of the control signal CONT outputted from the inverter12 is inputted to a gate 13a of the P channel MOS transistor 13. Thecontrol signal CONT is inputted to a gate 14a of the N channel MOStransistor 14.

FIG. 3 is a block diagram showing a structure example of the amplitudedetecting section 2 shown in FIG. 1.

As shown in FIG. 3, the amplitude detecting section 2 includes an Hlevel detecting circuit 21, an L level detecting circuit and a voltagedifferential detecting circuit 23.

The H level detecting circuit 21 detects a peak voltage (H levelvoltage) of an H level side of the clock signal CLK inputted from theoutside. The H level detecting circuit 21 outputs the signalcorresponding to the detected H level voltage to the voltagedifferential detecting circuit 23.

The L level detecting circuit 22 detects a bottom voltage (L levelvoltage) of an L level side of the clock signal CLK inputted from theoutside. The L level detecting circuit 22 outputs the signalcorresponding to the detected L level voltage to the voltagedifferential detecting circuit 23.

The voltage differential detecting circuit 23 detects the differencebetween the H level voltage and the L level voltage based on the twosignals outputted from the H level detecting circuit 21 and the L leveldetecting circuit 22. The voltage differential detecting circuit 23outputs the signal indicative of the difference to the comparator 3 asthe amplitude signal Va.

Operations of the clock buffer circuit 50 having the above mentionedstructure will be described below.

FIGS. 4A to 4E are timing charts to explain the operations of the clockbuffer circuit 50 shown in FIGS. 1 to 3.

At first, when an H level signal as the reset signal RST is inputted tothe reset input terminal R of the flip-flop 4, the flip-flop 4 is reset(Time T1). Accordingly, an H level signal is outputted, as the controlsignal CONT, from the inversion output terminal (/Q). Next, when a Llevel signal as the reset signal RST is inputted to the reset inputterminal R at a time T2, the reset state of the flip-flop 4 is released.

Immediately after the L level signal as the reset signal RST is inputtedand thereby the reset state of the flip-flop 4 is released (before theclock signal CLK and the clock input signal CRS are inputted), the stateof the flip-flop 4 is equal to the reset state. As the result, the Hlevel signal as the control signal CONT is outputted from the inversionoutput terminal (/Q) of the flip-flop 4 to the amplifier section 1.

When the control signal CONT at the H level is inputted to the amplifiersection 1, a L level signal is inputted to the gate 13a of the P channelMOS transistor 13, and also an H level signal is inputted to the gate14a of the N channel MOS transistor 14. Accordingly, the analog switch15 becomes in the ON state, and thereby the feedback loop 17 of theinverting amplifier 11 is generated.

If the feedback loop 17 of the inverting amplifier 11 is generated asmentioned above, when the clock signal CLK is amplified by the amplifiersection 1, a predetermined current flows through the analog switch 15constituting the feedback loop of the inverting amplifier 11. In thiscase, the predetermined current is determined by a resistance in the ONstate of the analog switch 15 itself. At this time (before a time T3described later), the clock signal CLK is not still inputted to theinverting amplifier 11 and the amplitude detecting section 2. As theresult, the level of the amplitude signal Va outputted from theamplitude detecting section 2 is fixed to the L level. Therefore, thelevel of the comparison result signal (the clock input signal) CRSoutputted from the comparator 3 is also the L level.

When the clock signal CLK is inputted from the outside at a time T3, theamplitude detecting section 2 detects the peak voltage of the H level ofthe inputted clock signal CLK and the bottom voltage of the L level ofthat, respectively. Then, the amplitude detecting section 2 outputs theamplitude signal Va based on the detected results (Time T4).

Next, the comparator 3 compares the voltage corresponding to theamplitude signal Va with the predetermined comparison voltage VREF tooutput the comparison result signal (the clock input signal) CRS (TimeT5).

If the voltage corresponding to the amplitude signal Va is higher thanthe predetermined comparison voltage VREF, namely, if the amplitude ofthe clock signal CLK is large enough to operate the semiconductorintegrated circuit, the level of the comparison result signal CRSchanges from the L level to the H level (Time T5). As the result, the Hlevel signal as the clock input signal CRS is inputted to the clockinput terminal C of the flip-flop 4. This causes the power supplyvoltage VDD to be connected (applied) to an output terminal (Q) (notshown) of the flip-flop 4. Therefore, the level of the output terminal(Q) becomes the H level similarly to the data input signal H. As theresult, the level of the signal outputted as the control signal CONTfrom the inversion output terminal (/Q) changes from the H level to theL level (Time T6).

When the level of the control signal CONT becomes the L level, the Hlevel signal is inputted to the gate 13a of the P channel MOS transistor13, and further the L level signal is inputted to the gate 14a of the Nchannel MOS transistor 14. This causes the analog switch 15 to be in theOFF state, and results in the state at which the feedback loop 17 of theinverting amplifier 11 is not generated (cut off) (Time T6).

This state at the time T6 is maintained, until the reset signal RST atthe H level is inputted to the reset input terminal R and the flip-flop4 is reset.

On the other hand, as shown in FIGS. 5A to 5E, if it is judged at thetime T4 that the voltage corresponding to the amplitude signal Vaoutputted from the amplitude detecting section 2 is lower than thepredetermined comparison voltage VREF, namely, if the amplitude of theclock signal CLK inputted from the outside is not large enough tooperate the semiconductor integrated circuit, the comparison resultsignal CRS outputted from the comparator 3 remains in the L level (TimeT5). As the result, the level of the signal outputted as the controlsignal CONT from the inversion output terminal (/Q) also remains in theH level.

If the control signal CONT consecutively remains in the H levelabove-mentioned, the analog switch 15 of the amplifier section 1 alsoremains in the ON state. Thus, the feedback loop 17 of the invertingamplifier 11 is consecutively generated.

(Another Embodiment)

FIG. 6 is a block diagram showing another structure example of theamplitude detecting section 2 shown in FIG. 1.

As shown in FIG. 6, the amplitude detecting section in a secondembodiment is constituted by a smoothing circuit 31. The smoothingcircuit 31 smooths the clock signal CLK inputted from the outside, andthen converts into a direct current voltage corresponding to anamplitude of the clock signal CLK to output as the amplitude signal Va.The comparator 3 compares the voltage corresponding to the amplitudesignal Va outputted from the smoothing circuit 31 with the predeterminedcomparison voltage VREF. The operations similar to those in the abovementioned embodiment are performed, on the basis of the comparisonresult.

In this embodiment, when the clock signal CLK is inputted from theoutside, the amplitude signal Va corresponding to the amplitude of theinputted clock signal CLK is firstly generated. The amplitude signal Vais compared with a signal indicative of a predetermined standard value.The control signal CONT is generated based on the comparison result. Inan amplifier section for amplifying the clock signal CLK, a switchprovided in the amplifier section is switched in response to the controlsignal CONT to suppress the current consumption of the amplifiersection.

The amplitude signal Va is generated in the amplitude detecting section2, and indicates the voltage corresponding to the amplitude of the clocksignal CLK. The amplitude signal Va is outputted to the comparator 3.The comparator 3 compares the voltage corresponding to the amplitudesignal Va inputted from the amplitude detecting section 2 with thepredetermined comparison voltage VREF to generate the control signalCONT corresponding to the comparison result.

The clock signal CLK is amplified on the basis of the control signalCONT, and outputted as a clock signal to the semiconductor integratedcircuit. If the clock signal CLK is given through, for example, acondenser coupling connection circuit from a small amplitude oscillator,such as TCXO, the voltage corresponding to the amplitude signal Va canbe lower than the predetermined comparison voltage VREF. In this case,the amplifier section 1 functions as the normal clock buffer circuit togenerate the feedback loop of the inverting amplifier 11 provided in theamplifier section 1.

On the other hand, if the clock signal CLK is given directly from adevice such as a CMOS transistor, the voltage corresponding to theamplitude signal Va can be higher than the predetermined comparisonvoltage VREF. In this case, the feedback loop of the inverting amplifier11 is released. Therefore, the useless current is never consumed, if theclock signal CLK whose amplitude is large enough to operate thesemiconductor integrated circuit is inputted to the clock buffer circuit50.

As mentioned above, in this embodiment, the feedback loop of theinverting amplifier 11 provided in the amplifier section 1 is generatedif the voltage corresponding to the amplitude signal Va is lower thanthe predetermined comparison voltage VREF. On the other hand, thefeedback loop of the inverting amplifier 11 is released if the voltagecorresponding to the amplitude signal Va is higher than thepredetermined comparison voltage VREF. Thus, the consumption of currentflowing through the clock buffer circuit 50 can be reduced if the clocksignal CLK whose amplitude is high enough to operate the semiconductorintegrated circuit is inputted to the clock buffer circuit 50.

Incidentally, as shown in FIG. 7, it may be considered that an innerline 17 (corresponding to the feedback loop 17 in the above-mentionedembodiment) connected between an input side and an output side of anamplifier 11a is used as a bypass line. The clock signal CLK may bebypassed from the amplifier 11a through the bypass line 17, if theamplitude of the clock signal CLK inputted from the outside is highenough for the clock signal CLK not to need to be amplified. Thisenables the current consumption to be suppressed. In this case, ananalog switch 15 and the inner line 17 constitute a bypassing section.The bypassing section bypasses the clock signal CLK from the amplifier11a to prevent the amplifier 11a from being operated. At this time, theoperations of the amplifier 11a and the bypassing sections 15, 17 areselectively performed on the basis of the control signal CONT.

What is claimed is:
 1. A clock buffer circuit comprising:a. an amplifiersection for amplifying a clock signal in response to a control signal;and b. a control section for generating said control signal based on anamplitude of said clock signal, said control section comprising, anamplitude detecting section for detecting said amplitude of said clocksignal, a comparator for comparing said amplitude of said clock signalwith a Predetermined value, and a control signal generating section forgenerating said control signal based on said comparison result.
 2. Aclock buffer circuit according to claim 1, wherein said amplifiersection comprises:an amplifier for receiving said clock signal; a lineconnected between an output and an input of said amplifier; and aswitching section provided on said line, and wherein said switchingsection is turned ON/OFF in response to said control signal.
 3. A clockbuffer circuit according to claim 2, wherein said switching sectioncomprises a P channel MOS transistor and an N channel MOS transistor, asource of said P channel MOS transistor being connected to a source ofsaid N channel MOS transistor and a drain of said P channel MOStransistor being connected to a drain of said N channel MOS transistor,andwherein an inverter is connected to one of a gate of said P channelMOS transistor or a gate of said N channel MOS transistor, and saidcontrol signal is inputted to said inverter and to the other of saidgate of said P channel MOS transistor or said gate of said N channel MOStransistor.
 4. A clock buffer circuit according to claim 1, wherein saidamplitude detecting section comprises:a high level detecting section fordetecting a peak voltage in a high level of said clock signal; a lowlevel detecting section for detecting a bottom voltage in a low level ofsaid clock signal; and a voltage difference detecting section fordetecting a voltage difference between said peak voltage and said bottomvoltage as said amplitude of said clock signal.
 5. A clock buffercircuit according to claim 1, wherein said amplitude detecting sectioncomprises a smoothing circuit for smoothing said clock signal to convertsaid clock signal into a direct current voltage corresponding to saidamplitude of said clock signal.
 6. A clock buffer circuit according toclaim 1, wherein said control signal generating section comprises aflip-flop, andwherein said flip-flop comprises: a clock input terminalto which a signal indicative of said comparison result is inputted; adata input terminal to which a data input signal corresponding to apower supply voltage is inputted; a reset input terminal to which areset signal is inputted; and an inversion output terminal, and whereinsaid flip-flop outputs said control signal from said inversion outputterminal based on said signal indicative of said comparison result, saiddata input signal and said reset signal.
 7. A clock signal bufferingmethod, comprising the steps of:a. comparing a clock signal with areference signal to generate a control signal generating signal based onsaid comparison result, wherein the comparing step includes, detectingan amplitude of said clock signal, and comparing said amplitude of saidclock signal with a predetermined value corresponding to said referencesignal to generate said control signal generating signal based on saidcomparison result; b. generating a control signal based on said controlsignal generating signal; and c. outputting said clock signal inresponse to said control signal.
 8. A clock signal buffering methodaccording to claim 7, wherein the step of detecting said amplitude ofsaid clock signal includes:detecting a peak voltage in a high level ofsaid clock signal; detecting a bottom voltage in a low level of saidclock signal; and detecting a voltage difference between said peakvoltage and said bottom voltage as said amplitude of said clock signal.9. A clock signal buffering method according to claim 7, wherein thestep of detecting said amplitude of said clock signal includes smoothingsaid clock signal to convert into a direct current voltage correspondingto said amplitude of said clock signal.
 10. A clock signal bufferingmethod according to claim 7, wherein the step of outputting said clocksignal comprises:providing an amplifier to which said clock signal isinputted; providing a line connected between an output and an input ofsaid amplifier; providing a switching section provided on said line; andturning said switching section ON/OFF in response to said controlsignal.
 11. A clock buffer circuit comprising:a. means for comparing aclock signal with a reference signal to generate a control signalgenerating signal based on said comparison result, wherein the comparingmeans includes, means for detecting an amplitude of said clock signal,and means for comparing said amplitude of said clock signal with apredetermined value corresponding to said reference signal to Generatesaid control signal generating signal based on said comparison result;b. means for generating a control signal based on said control signalgenerating signal; and c. means for outputting said clock signal inresponse to said control signal.
 12. A clock buffer circuit according toclaim 11, wherein said means for detecting said amplitude of said clocksignal includes:means for detecting a peak voltage in a high level ofsaid clock signal; means for detecting a bottom voltage in a low levelof said clock signal; and means for detecting a voltage differencebetween said peak voltage and said bottom voltage as said amplitude ofsaid clock signal.
 13. A clock buffer circuit according to claim 11,wherein said means for detecting said amplitude of said clock signalsmooths said clock signal to convert into a direct current voltagecorresponding to said amplitude of said clock signal.
 14. A clock buffercircuit according to claim 11, wherein said means for outputting saidclock signal includes:means for providing an amplifier to which saidclock signal is inputted; means for providing a line connected betweenan output and an input of said amplifier; means for providing aswitching section arranged on said line; and means for turning saidswitching section ON/OFF in response to said control signal.
 15. A clockbuffer circuit comprising:an amplifier section for amplifying a clocksignal; and a control section for generating a control signal based onan amplitude of said clock signal, and wherein a feedback loop which canbe set in one of an opened state or a conductive state is arranged insaid amplifier section and said feedback loop is set selectively in oneof said opened state or said conductive state based on said controlsignal.
 16. A clock buffer circuit according to claim 15, wherein saidcontrol section includes:an amplitude detecting section for detectingsaid amplitude of said clock signal; a comparator for comparing saidamplitude of said clock signal with a predetermined value; and a controlsignal generating section for generating said control signal based onsaid comparison result.
 17. A clock buffer circuit according to claim16, wherein said amplitude detecting section includes:a high leveldetecting section for detecting a peak voltage in a high level of saidclock signal; a low level detecting section for detecting a bottomvoltage in a low level of said clock signal; and a voltage differencedetecting section for detecting a voltage difference between said peakvoltage and said bottom voltage as said amplitude of said clock signal.18. A clock buffer circuit according to claim 16, wherein said amplitudedetecting section includes a smoothing circuit for smoothing said clocksignal to convert into a direct current voltage corresponding to saidamplitude of said clock signal.
 19. A clock buffer circuit according toclaim 16, wherein said control signal generating section comprises aflip-flop, andwherein said flip-flop includes: a clock input terminal towhich a signal indicative of said comparison result is inputted; a datainput terminal to which a data input signal corresponding to a powersupply voltage is inputted; a reset input terminal to which a resetsignal is inputted; and an inversion output terminal, and wherein saidflip-flop outputs said control signal from said inversion outputterminal based on said signal indicative of said comparison result, saiddata input signal and said reset signal.
 20. A clock buffer circuitcomprising:an output section for receiving a clock signal, andselectively outputting one of said clock signal or an amplified clocksignal obtained by amplifying said clock signal in response to a controlsignal; and a control section for generating said control signal basedon an amplitude of said clock signal, and wherein said output sectionincludes: an amplifier for amplifying said clock signal; and a bypassingsection for bypassing said amplifier for said clock signal in responseto said control signal to prevent the amplifier from being operated,wherein the bypassing section comprises a feedback loop which can be setin one of an opened state or a conductive state arranged in saidamplifier, and said feedback loop is set selectively in one of saidopened state or said conductive state based upon said control signal.21. A clock buffer circuit, comprising:an input section for inputting aclock signal; and a control section for controlling a signal path forsaid clock signal to be set in one of a conductive state or anon-conductive state based on an amplitude of said clock signal, whereinthe control section comprises a feedback loop which can be set in one ofan opened state or a conductive state arranged in said control section,and said feedback loop is set selectively in one of said opened state orsaid conductive state based upon said control signal.